1. What is the difference between PLD, CPLD and FPGA?
Answer: The names of different manufacturers are different. PLD is the general term for programmable logic devices. The early multi-EEPROM process is based on the product term structure. FPGA refers to field programmable gate array, first invented by Xilinx. Mostly SRAM technology, based on the lookup table structure, EPROM for external configuration. Xilinx calls the SRAM process, the PLD of the EPROM to be configured externally as FPGA, and the PLD of the Flash process and product term structure as CPLD; Altera calls its PLD products: MAX series, FLEX / ACEX / APEX series as CPLD. Complex PLD, because the FLEX / ACEX / APEX series is also a SRAM process, the EPROM used for external configuration, the usage is the same as Xilinx FPGA, so many people call Altera's FELX / ACEX / APEX series products also called FPGA.
2. What kind of processor is NiosII embedded processor? What functions does it have compared to others?
Answer: 1) The Nios II embedded processor is a user-configurable general-purpose RISC embedded processor. Its ease of use and flexibility make it one of the most popular embedded processors in the world.
2) The Cyclone II FPGA series is the right choice for extremely price-sensitive applications because it provides the lowest single LE price compared to all other cost-optimized FPGA series. Each Cyclone II device is designed with the best set of features, including: â— Up to 68,416 LE for high-density applications, up to 1.1 megabit embedded processor for general storage â— Up to 150 18x18 embedded processing For low-cost digital signal processing (DSP) applications â— Dedicated external memory interface circuit to connect DDR2, DDR and SDR SDRAM and QDRII SRAM memory devices â— Up to 4 embedded PLLs for on-chip and off-chip system clock management â— Support single-ended I / O standard for 64-bit / 66-MHz PCI and 64-bit / 100-MHz PCI-X (mode 1) protocols â— With differential I / O signals, support RSDS, mini-LVDS, LVPECL and LVDS, data rate up to 805 megabits per second (Mbps) at the receiving end, up to 622Mbps at the sending end â— Automatic CRC detection for security-sensitive applications â— With support for fully customized Nios? II embedded processor â— Low serial configuration device Cost configuration solution â— Free IP function evaluation can be performed through the OpenCore Plus evaluation function of Quartus II software â— Quartus II Web Edition software provides free software support.
3. I originally had a 74-series circuit designed to work normally. Why doesn't it work after integrated into the PLD intact? Is there a problem with the chip?
Answer: There is a difference between designing PLD / FPGA internal circuits and designing 74 discrete circuits. This problem is caused by a glitch in the circuit. Different circuit wiring lengths cause inconsistent delays, competition and risk, and glitches. Distributed capacitance and inductance between discrete components can filter out these glitches, so when designing circuits with discrete components, competition risk and glitch issues are rarely considered, but there is no distributed capacitance and inductance inside PLD / FPGA, and any glitches cannot be filtered out ( Even if only 1ns). Some glitches can be ignored, and some are fatal (such as the clk, clr, and PRN terminals of the D flip-flop). These fatal glitches will cause the circuit to not work properly. This is the biggest difference between designing FPGAs and designing discrete components. Can modify the circuit to reduce harmful glitches. According to experience, almost all stability or reliability problems are caused by unreasonable internal circuit design of PLD.
4. How to delay the signal?
Answer: When it is necessary to delay a certain signal for a certain period of time, beginners often connect some NOT gates or other gate circuits in series after this signal. This method is feasible in the separation circuit. But in FPGA, the development software will remove these gates as redundant logic during the comprehensive design, and the delay effect cannot be achieved. When developing FPGA with ALTERA's MaxplusII, some delays can be generated by inserting some LCELL primitives, but the delay formed in this way is not stable in the FPGA chip, and will change with the change of external environment such as temperature. This is not advocated. Here, you can use a high-frequency clock to drive a shift register, wait for the delayed signal as the data input, set the number of stages of the shift register correctly according to the required delay, and the output of the shift register is the delayed signal. The delay signal generated by this method has an error compared with the original signal, and the size of the error is determined by the period of the high-frequency clock. For the delay of the data signal, you can use the data clock to resample the delayed signal at the output to eliminate the error.
5. What is an IP core or IP library? What types are there?
Answer: IP core refers to: design some function blocks that are commonly used in digital circuits but more complicated, such as FIR filter, SDRAM controller, PCI interface, etc., into modules that can modify parameters, so that other users can directly call these modules This will greatly reduce the burden on engineers and avoid duplication of labor. As the scale of CPLD / FPGA becomes larger and the design becomes more and more complex, the use of IP cores is a development trend. However, most libraries are currently charged.
6. How to design the power supply of 3.3V, 2.5V and other low voltage PLD / FPGA?
Answer: Low-dropout linear regulators (LDOs) are often used or switching power supplies are used. For details, see the power supply design of low-voltage PLD / FPGA.
7. How is the macro unit of CPLD / FPGA defined? How many gates does a macro cell correspond to?
Answer: Macro unit (or logic unit) is the most basic unit of PLD / FPGA. Different products call this basic unit differently, such as LE, MC, CLB, Slices, etc., but each basic unit generally includes two parts , One part implements combinational logic, and the other part implements sequential logic. The definition of each manufacturer may be different. For the chip of ALTERA, each basic unit contains a trigger; for some chips of Xilinx, each basic unit unit contains two triggers. Generally, the number of "gates" is not used to measure the size of the PLD / FPGA, because the algorithms for the number of gates are different from each other. The calculation results of the gates like ALTERA and Xilinx are doubled. It is recommended to use the number of triggers to measure the size of the chip. For example, Xilinx's XC2S100 of 100,000 gates has 1200 slices, that is, contains 2400 triggers; 50,000 gates of ALTERA's 1K50 contains 2880 LEs, or 2880 triggers.
8. Why are some programs written according to the standard VHDL grammar fail to compile under Maxplus II?
Answer: MaxplusII supports most of the VHDL syntax, but there are also some standard VHDL statements that cannot be supported. The best way is to use a special VHDL language synthesis tool to synthesize, generate * .edif files and then wire MaxplusII. Altera has reached a cooperation agreement with Synopsys and Mentor since May 2000. All Altera users can use the following special VHDL tools for free according to the agreement: 1. Synopsys FPGA Express (HDL synthesis tool) 2. Mentor Graphics' Leonard Spectrum (HDL) Comprehensive tool) 3. Mentor ModelSim (HDL simulation tool), the software can be downloaded from Altera's Internet. 9. How to set the clock period and total simulation time during simulation?
After the simulation window appears, the menu: Option> snap to the grid must be unchecked to set the clock frequency arbitrarily, and the simulation time can be modified in the menu File> End time. The longer the simulation time, the greater the memory and CPU requirements.
9. FLEX10K / ACEX series devices can do various RAM and ROM, so how to initialize ROM?
Answer: When calling in the ROM component (available in LPM_ROM or using MegaWizard Plug-In Manager), the software will ask for the name of the initialization file. If you have not done this file, you can fill in a file name first, such as: test.mif or test.hex (the file test does not exist now), compile after completing the design, then create the waveform file * .SCF, open the simulation window simulator, at this time you can find Initialize> Initialize Memory in the menu (this option only appears in the simulation window It will appear later) At this time, you can edit the initialization file and output it as a * .mif or * .hex file (such as test.mif or test.hex). This is considered complete.
10. How to calculate power consumption and supply current?
Answer: Users of QuartusII can directly use QuartusII to calculate power consumption. Users of MaxplusII can use several Excel applets here to automatically calculate power consumption and current. Interested users may wish to download and try it. If some parameters are unclear, please refer to Altera Date BooK.
1) MAX7000 data sheet 2) FLEX10K / 6K data sheet
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